Introduction:
This is the project from Embedded System II class that we are designing both hardware and software platform. For the purpose of this particular project, we are required to create two IP modules using VHDL code to create a hardware function of capture and generate PPM signals taken from RC controller that has 6 channels.

Skills & Knowledge Gained:

• Creating new IP module in Vivado.
• Writing VHDL code for IP module.
• Software and hardware simulation/testing.

Resources:

• Vivado 2018.3
• Eclipse SDK (Software Development Kit)
• ​Zedboard: Zynq-7000
• ModelSim
• HobbyKing RC-Controller

Capture PPM:

Generate PPM:

Introduction:
In this project, we integrated Embedded Linux on a Xilinx Zedboard FPGA with on board ARM processor core. With that, we uses the hardware pipeline from the Digital Camera project and by also using DMA, we access the video from the Linux Kernel and wrote another application for target finding as well as drivers and application to drive the USB missile launcher to shoot at the target.

Skills & Knowledge Gained:

• Writing USB Driver for Missile Launcher from USB Skeleton Code
• Setting up and building Embedded Linux to run on an FPGA board
• Writing sentry launcher application utilizing USB missile launcher and camera data through DMA

Resources:

• Vivado 2018.3
• Eclipse SDK (Software Development Kit)
• ​Zedboard: Zynq-7000
• USB Missile Launcher
• Vita-2000 Camera

USB Missile Launcher Driver for Linux:

Introduction:
This is the project from Embedded System II class that we are designing both hardware and software platform. For the purpose of this particular project, we are required to convert a Bayer image input from VITA-2000 camera into a full 24-bit RGB full color and then to 16-bit YCbCr video color. The 16-bit YCbCr output is then output to monitor using an HDMI cable. In this project, we did the color conversion using two different approach:

1. software color conversion
2. hardware color pipeline

As we can see from the video, software color conversion has a lower frame rate as compared to hardware pipeline that has decent frame rate. Lastly, we are required to write C code to implement features in digital camera such as taking pictures and switching to playback mode.

Skills & Knowledge Gained:

• Image conversion modeling using Matlab.
• Understanding Color Conversion: Grayscale, Bayer, RGB format, YCbCr format.
• The pros and cons of software vs hardware pipeline implementation.

Resources:

• Vivado 2018.3
• Eclipse SDK (Software Development Kit)
• ​Zedboard: Zynq-7000
• Matlab
• Vita-2000 Camera

System Block Diagram:


MATLAB Prototype of Bayer to RGB to YCbCr color conversion:

System Block Diagram:
Introduction:
In this project, we are implementing a 5-stage pipelined MIPS processor. The architecture shall support at least 6 MIPS standard instructions: ADD, ADDI, LW, SW, BEQ, J. Many of the components of processor are provided but primarily focuses would be understanding and connecting the whole pipeline processor using components given as well as building our own hazard detection, forwarding unit, branch comparator and setting up the main control.
For detailed software simulation results, please refer project write-up document above.

Skills & Knowledge Gained:

• Building a MIPS Pipelined and non-pipelined Microprocessor using ALU, Register, and Memory VHDL Files provided.

Resources:

• ModelSim
• Computer Organization And Design 5th Edition Textbook
• Quartus Prime (Optional)
• Pipeline Registers (if_id.vhd, id_ex.vhd, ex_mem.vhd, mem_wb.vhd)
• VHDL Sources (adder_32.vhd, ALU.vhd, and_2.vhd, branch_comparator.vhd, dmem.vhd, forwarding_unit.vhd, hazard_detection_unit.vhd, imem.vhd, main_control.vhd, mipsprocessor_pipe.vhd, mux4to1_32bit.vhd, mux21_1bit.vhd, mux21_5bit.vhd, mux21_32bit.vhd, pc_reg.vhd, register_file.vhd, sign_externder_16_32.vhd, sll_2.vhd)

MIPS 32-bit Pipelined Microprocessor:

Main source code for Mars Rover Prototype (Programming System side):